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Research outputs
A hardware implementation of the mechanism of multiprocessing [1999]
Tomasevic, Milo V
; Bojovic, Marija; Djordjevic, Jovan
Efficient one-dimensional forward and inverse discrete wavelet transformers [2018]
Savić, Goran ; Prokin, Milan ; Rajović, Vladimir ; Prokin, Dragana
Disk interface comparison and operating system file-caching investigation
[2003]
Djordjevic, Borislav S ; Miskovic, Stanislav
A novel firefly algorithm approach for efficient feature selection with COVID-19 dataset
[2023]
N. Bacanin ; K. Venkatachalam; T. Bezdan ; M. Zivkovic ; M. Abouhawwash
Hardware implementation of DIRLS mismatched compressor applied to a pulse-Doppler radar system [2013]
Simić, Slobodan ; Zejak, Aleksa ; Golubičić, Zoran
An improved algorithm for the estimation of the root mean square value as an optimal solution for commercial measurement equipment
[2024]
Bulat, Marina ; Mirković, Stefan ; Gazivoda, Nemanja ; Pejić, Dragan ; Urekar, Marjan ; Antić, Boris
A performance evaluation of cache injection in bus-based shared memory multiprocessors [2002]
Milenkovic, Aleksandar; Milutinovic, Veljko M
E2LP: A unified embedded engineering learning platform
[2014]
Kaštelan, Ivan ; Lopez, Benito Jorge R.; Artetxe, Gonzalez Enara; Piwinski, Jan; Barak, Moshe; Temerinac, Miodrag
Co-Processor for evolutionary full decision tree induction
[2016]
Vukobratović, Bogdan Z.; Struharik, Rastislav
The Word-invalidate Cache Coherence Protocol [1996]
M. Tomašević ; V. Milutinović
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