Researchers
Stojčev, Mile
Issue Date | Title | Author(s) | Type | М-cat. |
---|---|---|---|---|
2017 | Implementation and evaluation of 2D SEC-DED forward error correction scheme in wireless sensor networks | Nikolić, Goran ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() | Article | 22M22 |
2016 | Reliable data transfer Rendezvous protocol in wireless sensor networks using 2D-SEC-DED encoding technique | Nikolić, Goran ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() | Article | 22M22 |
2015 | Low-power fault-tolerant interconnect method based on LCDMA and duplication | Nikolić, Tatjana ![]() ![]() ![]() ![]() ![]() | Article | 22M22 |
2015 | Improving fault-tolerance capability of on-chip binary CDMA bus | Nikolić, Tatjana ![]() ![]() ![]() ![]() ![]() ![]() ![]() | Article | 22M22 |
2014 | RPATS – Reliable power aware time synchronization protocol | Kosanovic, Mirko R.; Stojčev, Mile ![]() | Article | 22M22 |
2011 | Orthogonal fault-tolerant systolic arrays for matrix multiplication | Milovanović, Igor ![]() ![]() ![]() ![]() ![]() | Article | 22M22 |
2010 | Address generators for linear systolic array | Stojčev, Mile ![]() ![]() ![]() ![]() ![]() ![]() ![]() | Article | 22M22 |
2009 | Multi-functional systolic array with reconfigurable micro-power processing elements (✓) | Milovanović, Emina ![]() ![]() ![]() ![]() ![]() ![]() ![]() | Article | 22M22 |
2009 | CDMA bus-based on-chip interconnect infrastructure (✓) | Nikolić, Tatjana ![]() ![]() ![]() ![]() ![]() | Article | 22M22 |
2004 | Approach to partially self-checking combinational circuits design (✓) | Đorđević, Goran ![]() ![]() ![]() ![]() ![]() | Article | 22M22 |
2004 | Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits (✓) | Stojčev, Mile ![]() ![]() ![]() ![]() ![]() | Article | 22M22 |