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Research outputs

The loop shaping design procedure for parallel operating dc/dc converters   [2000]

T. B. Petrović; A. Ž. Rakić  ; S. L. Korać

Efficient and realistic statistical worst case delay computation using VHDL   [2009]

Sokolovic, Miljana; Litovski, Vanco B; Zwolinski, Mark

Analysis of faults in active distribution network with and without synchronous generator using instantaneous symmetrical components in time domain   [2018]

Mijailović, Vladica  ; Ćetenović, Dragan  ; Ranković, Aleksandar  ; Petrović, Predrag  ; Rozgić, Dimitrije  

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