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eNauka >  Results >  Novel Memory Efficient Hardware Architecture for 5/3 Lifting-Based 2D Inverse DWT
Title: Novel Memory Efficient Hardware Architecture for 5/3 Lifting-Based 2D Inverse DWT
Authors: Savić, Goran  ; Rajović, Vladimir  
Issue Date: 2019
Publication: JOURNAL OF CIRCUITS, SYSTEMS, AND COMPUTERS
ISSN: 0218-1266 Journal of Circuits Systems and Computers Search Idenfier
Type: Article
Collation: vol. 28 br. 07 str. 1950118-1950118
DOI: 10.1142/s0218126619501184
WoS-ID: 000473358600014
Scopus-ID: 2-s2.0-85052960694
URI: https://enauka.gov.rs/handle/123456789/456251
http://zaposleni.etf.bg.ac.rs/rest/sciNaucniRezultati/oai/record/2/707218
URL: https://www.worldscientific.com/doi/abs/10.1142/S0218126619501184
Metadata source: Migracija
M-category: 
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