Optimization of modular reduction procedure in RSA algorithm implementation on assembler of TMS320C54x signal processors

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Naziv:	Optimization of modular reduction procedure in RSA algorithm implementation on assembler of TMS320C54x signal processors
Autori:	Djordjevic, G; Unkasevic, Tomislav ; Markovic, M
Godina:	2002
Publikacija:	DSP 2002: 14TH INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING PROCEEDINGS, VOLS 1 AND 2
Izdavač:	IEEE
Tip rezultata:	Konferencijski rad
ISBN:	0-7803-7503-3 Pretraži identifikator
Kolacija:	str. 811-814
DOI:	10.1109/ICDSP.2002.1028214
WoS-ID:	000179052600171
Scopus-ID:	2-s2.0-34547231029
URI:	https://enauka.gov.rs/handle/123456789/820766
Izvor metapodataka:	(Preuzeto iz Nasi u WoS)
M-kategorija:	Mp kategorija će biti prikazana naknadno.

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