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eNauka >  Results >  Optimization of the Binary Adder Architectures Implemented in ASICs and FPGAs
Title: Optimization of the Binary Adder Architectures Implemented in ASICs and FPGAs
Authors: Jovanović, Bojan  ; Jevtić, Milun
Issue Date: 2013
Publication: Soft Computing Applications
ISSN: 2194-5357 Search Idenfier
Type: Article
Collation: str. 295-308
DOI: 10.1007/978-3-642-33941-7_27
WoS-ID: 000314077300027
Scopus-ID: 2-s2.0-84872860733
URI: https://enauka.gov.rs/handle/123456789/558531
Metadata source: Migrirano iz RIS podataka
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