Delay Locked Loop Clock Generator in Low Power VLSI IC Design

Jovanović, Goran; Mitić, Darko B.; Stojčev, Mile; Antić, Dragan S.

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Title:	Delay Locked Loop Clock Generator in Low Power VLSI IC Design
Authors:	Jovanović, Goran ; Mitić, Darko B. ; Stojčev, Mile ; Antić, Dragan S.
Issue Date:	2011
Publication:	Transactions on AUTOMATIC CONTROL and COMPUTER SCIENCE
ISSN:	1224-600X Search Idenfier
Publisher:	Politehnica University of Timisoara, Romania
Type:	Article
Collation:	vol. 56(70) br. 4 str. 131-136
URI:	https://enauka.gov.rs/handle/123456789/188346
URL:	http://www.ac.upt.ro/journal/issues.php
Metadata source:	Migrirano iz RIS podataka
M-category:	Mp. category will be shown later

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