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eNauka >  Results >  Tuning Logic Simulator for Estimation of VLSI Timing Degradation under Aging
Title: Tuning Logic Simulator for Estimation of VLSI Timing Degradation under Aging
Authors: Milić, Miljana  
Issue Date: 2019
Publication: ADVANCES IN ELECTRICAL AND COMPUTER ENGINEERING
ISSN: 1582-7445 Advances in Electrical and Computer Engineering Search Idenfier
Type: Article
Collation: vol. 19 br. 3 str. 75-82
DOI: 10.4316/aece.2019.03009
WoS-ID: 000486574100009
Scopus-ID: 2-s2.0-85072177529
URI: https://enauka.gov.rs/handle/123456789/481142
Project: Ministry of Education and Science of Republic of Serbia [TR32004]
Metadata source: Migracija
M-category: 
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