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Symbolic analysis of faulty logic circuits in the presence of correlated gate failures
| Title: | Symbolic analysis of faulty logic circuits in the presence of correlated gate failures | Authors: | Brkić, Srđan  ; Ivaniš, Predrag  ; Đorđević, Goran ; Vasic, Bane |
Issue Date: | 2013 | Publication: | 21st Telecommunications Forum Telfor TELFOR 2013 | Publisher: | IEEE | Type: | Conference Paper | DOI: | 10.1109/telfor.2013.6716246 | WoS-ID: | 000349857500087 | Scopus-ID: | 2-s2.0-84894349289 | URI: | https://enauka.gov.rs/handle/123456789/484555 http://zaposleni.etf.bg.ac.rs/rest/sciNaucniRezultati/oai/record/3/707475 |
Project: | Seventh Framework Programme of the European Union,European Union (EU) [309129] National Science Foundation (NSF) [CCF-0963726, CCF-1314147] |
Metadata source: | Migracija | M-category: | Mp. category will be shown later |
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