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Using VHDL simulator to estimate logic path delays in combinational and embedded sequential circuits
| Title: | Using VHDL simulator to estimate logic path delays in combinational and embedded sequential circuits | Authors: | Sokolovic, Miljana; Litovski, Vanco B | Issue Date: | 2005 | Publication: | Eurocon 2005: The International Conference on Computer as a Tool, Vol 1 and 2 , Proceedings | Type: | Conference Paper | Collation: | str. 1683-1686 | WoS-ID: | 000237248900421 | URI: | https://enauka.gov.rs/handle/123456789/808296 | Metadata source: | (Preuzeto iz Nasi u WoS) | M-category: | Mp. category will be shown later |
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