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| Title: | Synthesizable SystemVerilog Assertions as a Methodology for SoC Verification | Authors: | Kastelan, Ivan   ; Krajacevic, Zoran |
Issue Date: | 2009 | Publication: | Eastern European Conference on the Engineering of Computer Based Systems (1; 2009; Novi Sad) | Publisher: | IEEE | Type: | Conference Paper | Collation: | str. 120-127 | DOI: | 10.1109/ECBS-EERC.2009.19 | WoS-ID: | 000274849200017 | Scopus-ID: | 2-s2.0-74349092267 | URI: | https://enauka.gov.rs/handle/123456789/819996 | Metadata source: | (Preuzeto iz Nasi u WoS) | M-category: | Mp. category will be shown later |
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