Rezultati

eNauka >  Results >  Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits
Title: Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits
Authors: Stojčev, Mile ; Đorđević, Goran  ; Stanković, Tatjana  
Issue Date: 2004
Publication: MICROELECTRONICS RELIABILITY
ISSN: 0026-2714 Microelectronics Reliability Search Idenfier
Type: Article
Collation: vol. 44 br. 1 str. 173-178
DOI: 10.1016/S0026-2714(03)00377-9
WoS-ID: 000188123700019
Scopus-ID: 2-s2.0-0347412042
URI: https://enauka.gov.rs/handle/123456789/829433
Metadata source: (Preuzeto iz Nasi u WoS)
M-category: 
22M22

18
SCOPUSTM
13
OpenCitations
10
WEB OF SCIENCETM
Alt metrika
Dimensions
Unpaywall

Rezultati na eNauka su zaštićeni autorskim pravima i sva prava su zadržana, osim ako nije drugačije naznačeno.