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eNauka >  Results >  VHDL realization of a hardware accelerator for k-NN classification
Title: VHDL realization of a hardware accelerator for k-NN classification
Authors: Jovanović, Milica  ; Đorđević, Milica; Đošić, Sandra  
Issue Date: 2023
Publication: 16-th International Conference on Advanced Technologies, Systems and Services in Telecommunications, TELSIKS 2023
Type: Conference Paper
DOI: 10.1109/telsiks57806.2023.10316120
Scopus-ID: 2-s2.0-85179620602
URI: https://enauka.gov.rs/handle/123456789/877253
Metadata source: (Preuzeto iz ORCID-a) Jovanović, Milica
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